This invention relates to a level conversion circuit for use in a semiconductor integrated circuit and, in particular, to a level shifter circuit for carrying out a level conversion on a low level.
As is well known in the art, metal oxide semiconductor (MOS) transistors are classified into N-channel MOS transistors and P-channel MOS transistors. Each N-channel transistor is formed on a P-well substrate while each P-channel transistor is formed on an N-well substrate. In addition, each MOS transistor has gate, drain, and source electrodes. Each MOS transistor may have a backgate electrode which is generally connected to the source electrode thereof.
In the manner which will later be described in conjunction with FIGS. 3A through 3E in detail, a conventional level shifter circuit comprises an inverter, first through sixth P-channel MOS transistors, and first through fourth MOS transistors. The inverter inverts an input signal to produce an inverted input signal. The first P-channel MOS transistor has a source electrode supplied with a power supply voltage and a gate electrode supplied with the input signal. The second P-channel MOS transistor has a source electrode supplied with the power supply voltage and a gate electrode supplied with the inverted input signal. The first N-channel MOS transistor has a drain electrode connected to a first node, a gate electrode connected to a second node, and a source electrode supplied with a level shift variable voltage. The second N-channel MOS transistor has a drain electrode connected to the second node, a gate electrode connected to the first node, and a source electrode supplied with the level shift variable voltage.
The third P-channel MOS transistor is connected between a drain electrode of the first P-channel MOS transistor and an inverting output terminal. The third P-channel MOS transistor has a gate electrode supplied with a switching signal. The third P-channel MOS transistor serves as a first breakdown preventing arrangement for preventing the first P-channel MOS transistor from breaking down. The fourth P-channel MOS transistor is connected between a drain electrode of the second P-channel MOS transistor and a non-inverting output terminal. The fourth P-channel MOS transistor has a gate electrode supplied with the switching signal. The fourth P-channel MOS transistor acts as a second breakdown preventing arrangement for preventing the second P-channel MOS transistor from breaking down.
The third N-channel MOS transistor is between the first node (the drain electrode of the first N-channel MOS transistor) and the inverting output terminal. The third N-channel MOS transistor serves as a first gate destruction preventing arrangement for preventing the gate electrode of the first N-channel MOS transistor from destroying. The fourth N-channel MOS transistor is between the second node (the drain electrode of the second N-channel MOS transistor) and the non-inverting output terminal. The fourth N-channel MOS transistor acts as a second gate destruction preventing arrangement for preventing the gate electrode of the second N-channel MOS transistor from destroying.
The fifth P-channel MOS transistor has a source electrode supplied with the switching signal, a gate electrode connected to the second node, and a drain electrode connected to the first node. The sixth P-channel MOS transistor has a source electrode supplied with the switching signal, a gate electrode connected to the first node, and a drain electrode connected to the second node. A combination of the fifth and the sixth P-channel MOS transistors is operable as an accelerating arrangement for accelerating a switching speed for signals.
However, a problem arises in the conventional level shifter circuit when the power supply voltage is a low voltage. This is because a signal switching for inverted and non-inverted output signals does not occur in the conventional level shifter circuit although a switching of the input signal is carried out in the manner which will later become clear.